職務說明 / Key Responsibilities
Working Location : Taipei / HsinChu
Job Description
1. SoC chip integration from RTL to gate level including timing closure and DFT
2. Digital design methodology integration and QC flow improvement
需求條件 / Key Requirements
擅長工具
MCU
ARM
ASIC
RTL
Verilog
工作技能
電子電路設計
電源管理IC設計
Requirement
1. Cell base IC design flow knowledge and experience
2. Digital IC design EDA tool and flow development experience
3. Basic RTL design experience and Timing/CTS/Physical concept
4. good script skill i.e. Per/Python/Tcl interested in programming
5. DFT knowledge and integration experience is plus
法定福利與權利
雇主依法應盡義務（含勞動基準法、性別平等工作法、全民健康保險法、勞工保險條例等）及員工依法應享權利（如勞健保、勞退、特別休假、婚假等）
載入中...
