職務說明 / Key Responsibilities
Responsibilities :
1.Responsible on STA / design constraint validation for advanced technology nodes.
2.Develop new Timing Signoff flow.
3.Co-work with PD owners for Project Timing Closure.
Requirements :
1.Ph.D or Master degree in EE or CS.
2.10+ years of experience in STA / Front-end domain.
3.Experience on tape-out advanced-node chips, i.e., 7nm and below.
4.Strong knowledge in IC design flow, microelectronics theory.
5.Expert-level signoff skill on Synopsys Primetime or Cadence Tempus
6.Strong technical capability in problem solving and researching.
需求條件 / Key Requirements
法定福利與權利
雇主依法應盡義務（含勞動基準法、性別平等工作法、全民健康保險法、勞工保險條例等）及員工依法應享權利（如勞健保、勞退、特別休假、婚假等）
載入中...
